In order to make grading the assignment easier, we will now make one change to the waveform result. Note: the imvaid input combinations may have slightly different results as they are don't cares. Your result should match the truth table. Review project 1 if you need help simulating your design 14. We can now simulate our design to make sure it matches the specification given in the truth table. If you hare to move a signal you can click and drag.ġ3. Add signals to the waveform using the "node-finder" make sure the signals are orderd correctly in the waveform windows (See image below). Note: you may want to review project1 or the recorded lecture on the University Program VWF. Go to File->new → >niversity Program vwt 7. Check the common quartus issues document to resolve this. If you get an "inst" error it means you have 2 components with the same name. Compile your design, once it shows everyahing breen we can test the design. Save your block diagram (remember filenames must start with a letter), make wure you change the project navigator drop down from "hierarchy" to "files", right click you bdf and "set to top level" 5. 2 -input NOR gates, 2 -input XOR, and 2 -input XNOR Eates in addition to the 4 inverters used to create A ′, A ′, C ′ and D ′ (nand2, nor 2, nor, ,nor in quartus) 4. Using labels to connect to the existing signals (A, B, C, D, Anot, Bnot, Cnot, Dnot, W, X, Y, Z, V, build the code-: converter using only 2 -input NAND. Once you are in a new project, create a new block diagram file (bdf) (remember filenames must start with a letter) Add 4 input pins and label them A, B, C, D from top to bottom Add 5 output pins and label the W, X, Y, Z, V from top to bottom You may use 4 "not" gates to create signals for Anot, Bnot, Cnot, and Dnot (See image below)ģ. If needed, review project 1 for details in creating a new blank project. Open Quartus and create a new project fin a new folder separate from Project 1: remember: ali projects must be in their own folders - folder names cancot have a space in them). I recommend you watch the lecture: "University Program VWF details" for extra info on the simulator. Part II: Quartus Simulation Note: Filenames and folder names carinot contain spaces or special characters other than _ AND MUST START WITH A LETTER Note2: Be sure that project 2 is in its own foider separate from project 1 and that all of your bof and vwi files are in that folder when simulating. 2-input NOR Eates, 2-input XOR and 2 -input XNOR gates in addition to the 4 inverters used to create A ′, B ′, C ′ and D ′ We will use this implementation in our Quartus Circuit in PART II. Minimize each expression and convert your result to use only 2-input NAND gates. Fill out the 5 KMAPS on the template to find minimal SOP for each output. Remember to include the don't care terms as well. Using the table abeve, find sum of minterm form for W, X, Y, Z, and V. Fill out the valid-bit for the above code converter.
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